TY - CHAP
T1 - Wearable FPGA Platform for Accelerated DSP and AI Applications
AU - Roggen, Daniel
AU - Cobden, Robert
AU - Pouryazdan, Arash
AU - Zeeshan, Muhammad
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022/3/21
Y1 - 2022/3/21
N2 - Some algorithms benefit from a hardware digital logic implantation to achieve higher speed or to meet specific timing requirements, such as in digital signal processing, digital communication, and also when investigating hardware-accelerated machine learning algorithms. We present an extensible, miniature, battery-operated Field Programmable Gate Array (FPGA) platform for wearable computing and IoT research, based on an Intel MAX10 FPGA. The platform is 30x30mm in size and can be used as a standalone device, or as an extension to a similarly sized microcontroller board, for example to pre-process high-speed data streams in hardware prior to relaying the data to a conventional processor. We present the FPGA board and characterise power consumption, resource usage, and processing speed for the implementation of elementary DSP operations, notably FIR filters. We also carry out a direct comparison of these metrics for the FIR algorithm running on an ARM Cortex M4 processor as well as a soft-core processor synthesized on the FPGA board. The results show that this miniature FPGA platform has sufficient logic gates and computing power for a wide class of digital communication algorithms. The platform hardware and firmware is available on GitHub.
AB - Some algorithms benefit from a hardware digital logic implantation to achieve higher speed or to meet specific timing requirements, such as in digital signal processing, digital communication, and also when investigating hardware-accelerated machine learning algorithms. We present an extensible, miniature, battery-operated Field Programmable Gate Array (FPGA) platform for wearable computing and IoT research, based on an Intel MAX10 FPGA. The platform is 30x30mm in size and can be used as a standalone device, or as an extension to a similarly sized microcontroller board, for example to pre-process high-speed data streams in hardware prior to relaying the data to a conventional processor. We present the FPGA board and characterise power consumption, resource usage, and processing speed for the implementation of elementary DSP operations, notably FIR filters. We also carry out a direct comparison of these metrics for the FIR algorithm running on an ARM Cortex M4 processor as well as a soft-core processor synthesized on the FPGA board. The results show that this miniature FPGA platform has sufficient logic gates and computing power for a wide class of digital communication algorithms. The platform hardware and firmware is available on GitHub.
KW - FPGA
KW - IoT
KW - Wearable computing
KW - digital signal processing
KW - embedded computing
UR - http://www.scopus.com/inward/record.url?scp=85130613061&partnerID=8YFLogxK
U2 - 10.1109/percomworkshops53856.2022.9767398
DO - 10.1109/percomworkshops53856.2022.9767398
M3 - Chapter
T3 - 2022 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events (PerCom Workshops)
SP - 66
EP - 69
BT - 2022 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events (PerCom Workshops)
ER -